Advanced Analog CMOS IC DesignAugust 26th – August 30st 2013 LEAFLET
APPLICATION for SCHOLARSHIP
The course will discuss the most important problems facing analog IC designers and their solutions on an advanced level. At the beginning, the course will deliberately insist on the deep understanding and adequate modeling of active components and of their basic combinations, which are considered to be prerequisites for sound analog design. The course will then cover operational amplifiers, voltage references, integrated analog filters and off-chip drivers. It will also discuss technology limitations and address the challenges of nanoscale CMOS physical design.
This course is accepted by the doctoral school of the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland. PhD students can be granted 3 ECTS credits after evaluation based upon a paper or an oral test on a theme to be agreed with the course program board.
This course fulfills all the criteria imposed by the FP7 EURO-DOTS program, and has been provisionally granted the EURO-DOTS label. PhD students fulfilling the requirements can apply for a scholarship. Details on the FP7 EURO-DOTS program, these requirements and the application procedure can be found on Students >> Rules.
WHO SHOULD ATTEND?The prerequisite for the course is a basic knowledge of semiconductor devices and circuits. It addresses the training needs of all electrical engineering community involved in microelectronics and nanoelectronics.
PhD students and members of academic institutes will particularly benefit from an up-date information for their current research and teaching. This course is intended for any IC design engineer already working in academia or semiconductor industry, technical supervisors, managers and directors working in, or having responsibilities for:
- IC design, layout and characterization
- Research and development
- Decision making for technology choice and architectures
- Projects completion
COURSE LOCATIONThe course will take place at the premises of the Federal Institute of Technology (EPFL), Lausanne, Switzerland. Route description
FEES AND REGULATIONSThe fee of EUR 2,300 includes all lectures, a complete set of course notes in electronic format, lunches and two daily coffee breaks. One social evening will be organized for all attendees and instructors of the course. The social evening is usually held on the Wednesday evening.
Discounted fee for PhD students: EUR 1000.
Registration deadline: July 15, 2013.
Payment deadline: August 16, 2013.
Hotel accommodations and meals other than lunches are note included in the course fee. Mead reserves the right to cancel the program up to one month before the start of the course and its liability is limited to a full refund of the course fee.
Fees will be fully refunded if a cancellation is received by the payment deadline. No refund will be issued for cancellation notices received after this date. Registration fees may be transferred to an alternative attendee or used to pay for participation in a future MEAD course. Unpaid registrants are responsible for fees unless a cancellation is received by the deadline for payment. All reimbursement will incur a 10% fee per course.
For any further information or to contact us please see our web site: www.mead.ch
Ph.D., Swiss Federal Institute of Technology, Lausanne, Switzerland (EPFL), 1969. He was engaged in the early developments of electronic watches since 1962 in CEH, where he was appointed Vice-Director in 1971. Since 1984, he has been with CSEM (Swiss Center of Electronics and Microtechnology) were he was Executive Vice-President, Advanced Micro-electronics until 1999. He is now fully retired from CSEM where he held the position of Chief Scientist. He is also professor at EPFL, has authored or co-authored more than 130 papers on low power, analog design, and analog VLSI computation, and holds 26 patents. A Life Fellow of IEEE, he is the recipient of the 2004 IEEE Solid-State Circuits Field Award.
B.S. Eng. (with academic honor) and M.S.E.E. California Institute of Technology; Ph.D. Stanford, 1984. His closed-form analytical solution for the MOS device surface potential at Stanford resulted in the first charge model that was continuous from weak to strong inversion. Past work includes the circuit and physical design of a 1.2 mW 16b x36-channel ADC currently used in the Hubble Space Telescope ACS camera. He is currently president of Lewyn Consulting Inc. (LCI) in Laguna Beach, CA and is a member of the technical advisory boards of the Snowbush-Gennum Physical Design Center in Aguascalientes Mexico, and the Tanner EDA Division of Tanner Research, Monrovia Ca. His work at LCI includes the design of a low-power, 12b 1GSPS ADC IP that is portable to the 45, 32 and 22 nm LP and HP technology nodes. He holds 29 patents in CMOS and bipolar circuits, and is a Life Senior Member of the IEEE.
Prof. Willy Sansen has an MSc Degree from the K.U.Leuven and a PhD degree from the University of California, Berkeley in 1972. Since 1980 he has been full professor at the Catholic University of Leuven, in Belgium, where he has headed the ESAT-MICAS laboratory on analog design since 1984. He has been supervisor of sixty-three PhD theses and has authored and coauthored more than 635 publications and sixteen books, among which “Analog Design Essentials” (Springer 2008). He is a Fellow of the IEEE. He was program chair of the ISSCC-2002 conference and is now Past-President of the IEEE Solid-State Circuits.
Ph.D., University of California, Berkeley. 1983-84. Visiting Professor at the University of Genova. From 1984 to 1986, Visiting Assistant Professor at the University of California, Berkeley. Since 2000 Full Professor with the Department of Electrical Engineering at the University of Pavia, Pavia, Italy, and a consultant with Marvell Technology, Pavia, Italy. Main interest in circuit design of telecommunications and analog/digital interfaces.
Received his MS in electronics from the Katholieke Universiteit Leuven in 1970. As assistant at the university, he worked on bipolar technology, device modeling and mixed signal design in bipolar and MOS technologies. From 1977 to 1980, he joined BARCO N.V. as senior designer and later became responsible for new technologies. In 1980, he was one of the founders of the design house INCIR in Belgium. From 1983 to 2002, he was with Alcatel Microelectronics, where he first held several design and R&D management positions and later became engineering officer. Until 1997 he was involved in high voltage and sensor interfaces in CMOS and BiCMOS and in the definition of high voltage technologies for automotive and industrial applications. From 1997 to 2002 he researched high speed wireline interfaces, high accuracy telecom circuits and the analog front-end of ADSL. Since 2002 and untill his retirement in 2007, he was an engineering fellow at AMI Semiconductor in Oudenaarde, Belgium. His current research interests are technology limitations, high voltage, smart power circuits, high accuracy sensor interfaces, ESD, EMC and other interference protections in CMOS and DMOS technologies.Gabor Temes
Ph.D., University of Ottawa, 1961. Professor, Electrical and Computer Engineering Department, Oregon State University, Professor Emeritus, UCLA. Formerly with UCLA, Ampex Corp., Stanford University and BNR. Life Fellow IEEE. He wrote many books and papers on circuit design and data converters. He received the Technical Achievement Award and the Education Award of the IEEE CAS Society, as well as the IEEE Centennial Medal. He is also the recipient of the 1998 IEEE Graduate Teaching Award and received the IEEE Millennium Medal and the IEEE/CAS Golden Jubilee Medal in 2000. the IEEE Gustav Robert Kirchhoff Award in 2006, and the IEEE Mac Van Valkenburg Award in 2009.
Monday, August 26th 2013
- 8h30-12h00 am
MOS and Bipolar: Modes of Operation and Models
Since the MOS transistor is the basic component of device-level analog circuit design, a strong emphasis will be given on its basic theory: structure and definitions; calculation of surface field and potential, total charge, mobile inversion charge, pinch-off voltage, gate capacitance. An analytical core model requiring only 3 parameters will be derived, which conserves the inherent symmetry of the device and describes its large signal behavior from weak to strong inversion. Channel length modulation, short and narrow channel effects, small signal DC and AC models, temperature effects, noise and matching properties will then be presented. The bipolar transistor will be addressed more superficially, within the framework of CMOS technologies: Ebers-Moll model, large and small signal characteristics, noise, temperature effects, vertical bipolar in CMOS, bipolar operation of MOS transistors, special bipolar structures added in BiCMOS.
- 1h30-3h00 pm
Passive Components and Parasitic Effects
Capacitors, resistors, MOS transistors operated as pseudo-resistors, diodes, parasitic channels, latch-up and gate protection.
- 3h30-5h00 pm
Basic Layout Techniques
The fact that signals in analog circuits are represented by physical values and cannot be regenerated along the processing path results in various requirements on the layout. Devices must be implemented with a wide variety of sizes and shapes. Controlled absolute values are only required when a change in signal representation is needed, whereas optimally matched devices are the foundation of sound analog design and will be discussed in details. Parasitic components and effects may distort the signals or introduce unwanted noise sources. Their dependence on layout will be examined with emphasis on the long range coupling from digital to low-level analog subcircuits.
Tuesday, August 27th 2013
- 8h30-10h00 am
Nanoscale CMOS Physical Design
One objective of this segment is to identify many factors adversely affecting successful nanoscale analog physical design. However, the primary objective is to propose methods for mitigating or overcoming many physical design problems, so that the future of deep-nanoscale analog CMOS looks a bit brighter. CMOS IC verification tools are identifying a wider range of circuit and physical design deficiencies. However at the 45nm technology node and beyond, the gap between pre- and post-layout simulation results is widening. Circuit and layout redesign effort wastes the semiconductor industries most valuable commodity, time to market. One key to the basic approach is to propose certain restrictions on device design at the initial circuit design stage, and another is to achieve increased regularity in the physical design at circuit layout.
- 10h30-12h00 am + 1h30-3h00 pm
Elementary Building Blocks
Current mirrors, differential pair, current references, analog switch, voltage gain cells, source follower, dynamic comparator, dynamic current mirror, principle of switched capacitors, current generation, voltage-to-current conversion, translinear circuits, strong-inversion squarer-divider.
- 3h30-5h00 pm
"Built-In" voltages available in silicon. Circuits extracting thermodynamic voltage kT/q. Circuit extracting the bandgap voltage. Principle and properties of the bandgap voltage reference and its implementation in CMOS.
Wednesday, August 28th 2013
- 8h30-12h00 am + 1h30-5h00 pm
Analog Functional Blocks
The lectures start with an introduction on merits of MOSTs versus bipolar transistors in the different positions of an operational amplifier. Then the design procedures are given for optimal op-amp design by means of the pole-zero position and Bode diagrams. A second-order Miller op-amp is discussed in great detail followed by a design procedure for third-order nested Miller op-amps. All of them are optimized towards high GBW, low noise and minimum power consumption. Finally a considerable number of other configurations are discussed and compared, among which a few very-low-voltage fully-differential operational amplifiers, involving internal common-mode feedback.
Thursday, August 29th 2013
- 8h30-12h00 am
CMOS Off-Chip Drivers
This lecture deals with circuits that are intended to realize the peripheral of some ASIC chip and therefore are optimized for a particular set of specifications. Different overall amplifier topologies are considered. In particular distinction is made between circuit with a DC feedback around the output stage and those that use only an ac feedback. The voltage follower as an output stage is considered together with some very linear configurations based on the follower. The common source push-pull as a large swing output stage is considered in great details. Gain, offset, linearity, speed and stability are analyzed for various possible implementations. Fully differential and more unconventional configurations are also shown. Finally, some examples of amplifiers realized in mixed technologies used in high voltage applications are given.
- 1h30-5h00 pm
Technology and other Limitations for Analog Design
This module focuses on complementary aspects of analog design. It starts with an overview and comparison of different technology variations and families and includes a detailed comparison of bipolar and MOS transistors. The second part discusses analog design limitations beyond SPICE such as random and non-random parameter variations, device breakdown and degradation and environmental effects at chip level.
Friday, August 30th 2013
- 8h30-10h00 am
Technology and other Limitations for Analog Design
- 10h30-12h00 am + 1h30-5h00 pm
Integrated Analog Filters: Active RC, GmC & SC Filters
Continuous-time integrated filter realization: active RC and GmC filters. Single-opamp stages: Sallen-Key, Rauch and Deliyannis filters. Multi-opamp stages: the Tow-Thomas biquad. Cascade and simulated-LC filter structures. Dynamic range and impedance scaling. MOSFET-C and GmC realizations. Tuning schemes. The SR filter. SC filters: tolerance properties, the SC integrator and biquads. Cascade and simulated-LC SC filter structures. Scaling. Nonideal effects and their correction.
Important message to the PhD students interested in a EURO-DOTS scholarship!!!
Unfortunately today, on July 15 2014, we have reached the total EURO-DOTS quota for 2014! Every new application for a scholarship will be put on a waiting list. In case applicants withdraw their application, the available scholarship will be granted to the first on this list, and so on, until the budget is fully exhausted. Please read the full document “Important message to the PhD students in Electrical/Electronic Engineering and to their Supervisors” on Students –What’s in for PhD Students?
Status EURO-DOTS on 15 July 2014
In the past 3.5 years 130 EURO-DOTS course modules have been organized on 60 relevant topics/themes. These were organized by 20 course providers from 11 countries. Over 250 lecturers were involved. More than 330 PhD students, from 19 European countries, have successfully applied for a scholarship. In 2014 38 Courses have been scheduled, 11 of which still have to take place at this very moment (15 July 2014). The calendar and information can be found on Courses. For more up-to-date information on the realizations and conclusions of EURO-DOTS, please go to “EURO-DOTS Conclusions” on Final Reports
EURO-DOTS Testimonials by students
More than 130 testimonials by students can be found on Testimonials of students. We invite you to read through these messages and by these be convinced of the benefit to PhD students of an initiative and project like EURO-DOTS!
EURO-DOTS Testimonials by Course Providers
Five Course Providers share their enthusiasm on the EURO-DOTS initiative and explain why they decided to contribute and be part of the game. You can find their testimonial on Testimonial of Course Providers
EURO-DOTS flyer and poster
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